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时钟发生器

CDC906

不推荐用于新设计

167MHz、LVCMOS、定制编程的 3-PLL 时钟合成器、倍频器和分频器

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数据表
CDC906 不推荐用于新设计
虽然我们会继续生产此产品供先前的设计使用，但不推荐在新设计中使用此产品。请考虑从这些替代产品中选择一款：
open-in-new 比较替代产品
功能优于比较器件，可直接替换
CDCE906 正在供货 167MHz、LVCMOS、可编程 3-PLL 时钟合成器/倍频器/分频器 CDCE906 is a P2P, drop-in replacement for CDC906

CDC906

不推荐用于新设计
数据表 立即订购

产品详情

Function Clock generator Output frequency (max) (MHz) 167 Input type Differential, LVCMOS, XTAL Output type LVCMOS Operating temperature range (°C) to Rating Catalog
Function Clock generator Output frequency (max) (MHz) 167 Input type Differential, LVCMOS, XTAL Output type LVCMOS Operating temperature range (°C) to Rating Catalog
TSSOP (PW) 20 41.6 mm² 6.5 x 6.4
  • High Performance 3:6 PLL based Clock Synthesizer / Multiplier / Divider
  • User Programmable PLL Frequencies
  • Easy In-Circuit Programming via SMBus Data Interface
  • Wide PLL Divider Ratio Allows 0-PPM Output Clock Error
  • Generates Precise Video (27 MHz or 54 MHz) and Audio System Clocks from Multiple Sampling Frequencies (fS = 16, 22.05, 24, 32, 44.1, 48, 96 kHz)
  • Clock Inputs Accept a Crystal or a Single-Ended LVCMOS or a Differential Input Signal
  • Accepts Crystal Frequencies from 8 MHz up to 54 MHz
  • Accepts LVCMOS or Differential Input Frequencies up to 167 MHz
  • Two Programmable Control Inputs [S0/S1] for User Defined Control Signals
  • Six LVCMOS Outputs with Output Frequencies up to 167 MHz
  • LVCMOS Outputs can be Programmed for Complementary Signals
  • Free Selectable Output Frequency via Programmable Output Switching Matrix [6x6] Including 7-Bit Post-Divider for Each Output
  • PLL Loop Filter Components Integrated
  • Low Period Jitter (Typical 60 ps)
  • Features Spread Spectrum Clocking (SSC) for Lowering System EMI
  • Programmable Center Spread SSC Modulation (±0.1%, ±0.25%, and ±0.4%) with a Mean Phase Equal to the Phase of the Non-Modulated Frequency
  • Programmable Down Spread SSC Modulation (1%, 1.5%, 2%, and 3%)
  • Programmable Output Slew-Rate Control (SRC) for Lowering System EMI
  • 3.3-V Device Power Supply
  • Commercial Temperature Range 0°C to 70°C
  • Development and Programming Kit for Easy PLL Design and Programming
    (TI Pro-Clock)
  • Packaged in 20-Pin TSSOP
  • Factory Programmable for Customized Default Settings are Available. Contact TI Sales Fordes for Further Details.
  • APPLICATIONS
    • Digital TV
    • Printer / Scanner
    • Set Top Box
    • Video / Audio

Pro-Clock is a trademark of Texas Instruments.
  • High Performance 3:6 PLL based Clock Synthesizer / Multiplier / Divider
  • User Programmable PLL Frequencies
  • Easy In-Circuit Programming via SMBus Data Interface
  • Wide PLL Divider Ratio Allows 0-PPM Output Clock Error
  • Generates Precise Video (27 MHz or 54 MHz) and Audio System Clocks from Multiple Sampling Frequencies (fS = 16, 22.05, 24, 32, 44.1, 48, 96 kHz)
  • Clock Inputs Accept a Crystal or a Single-Ended LVCMOS or a Differential Input Signal
  • Accepts Crystal Frequencies from 8 MHz up to 54 MHz
  • Accepts LVCMOS or Differential Input Frequencies up to 167 MHz
  • Two Programmable Control Inputs [S0/S1] for User Defined Control Signals
  • Six LVCMOS Outputs with Output Frequencies up to 167 MHz
  • LVCMOS Outputs can be Programmed for Complementary Signals
  • Free Selectable Output Frequency via Programmable Output Switching Matrix [6x6] Including 7-Bit Post-Divider for Each Output
  • PLL Loop Filter Components Integrated
  • Low Period Jitter (Typical 60 ps)
  • Features Spread Spectrum Clocking (SSC) for Lowering System EMI
  • Programmable Center Spread SSC Modulation (±0.1%, ±0.25%, and ±0.4%) with a Mean Phase Equal to the Phase of the Non-Modulated Frequency
  • Programmable Down Spread SSC Modulation (1%, 1.5%, 2%, and 3%)
  • Programmable Output Slew-Rate Control (SRC) for Lowering System EMI
  • 3.3-V Device Power Supply
  • Commercial Temperature Range 0°C to 70°C
  • Development and Programming Kit for Easy PLL Design and Programming
    (TI Pro-Clock)
  • Packaged in 20-Pin TSSOP
  • Factory Programmable for Customized Default Settings are Available. Contact TI Sales Fordes for Further Details.
  • APPLICATIONS
    • Digital TV
    • Printer / Scanner
    • Set Top Box
    • Video / Audio

Pro-Clock is a trademark of Texas Instruments.

The CDC906 is one of the smallest and powerful PLL synthesizer / multiplier / divider available today. Despite its small physical outlines, the CDC906 is flexible. It has the capability to produce an almost independent output frequency from a given input frequency.

The input frequency can be derived from a LVCMOS, differential input clock, or a single crystal. The appropriate input waveform can be selected via the SMBus data interface controller.

To achieve an independent output frequency the reference divider M and the feedback divider N for each PLL can be set to values from 1 up to 511 for the M-Divider and from 1 up to 4095 for the N-Divider. The PLL-VCO (voltage controlled oscillator) frequency than is routed to the free programmable output switching matrix to any of the six outputs. The switching matrix includes an additional 7-bit post-divider (1-to-127) and an inverting logic for each output.

The deep M/N divider ratio allows the generation of zero ppm clocks from any reference input frequency (e.g., a 27 MHz).

The CDC906 includes three PLLs of those one supports SSC (spread-spectrum clocking). PLL1, PLL2, and PLL3 are designed for frequencies up to 167 MHz and optimized for zero-ppm applications with wide divider factors.

PLL2 also supports center-spread and down-spread spectrum clocking (SSC). This is a common technique to reduce electro-magnetic interference. Also, the slew-rate controllable (SRC) output edges minimize EMI noise.

Based on the PLL frequency and the divider settings, the internal loop filter components is automatically adjusted to achieve high stability and optimized jitter transfer characteristic of the PLL.

The device provides customized applications. It is preprogrammed with a factory default configuration (see Figure 13) and can be reprogrammed to a different application configuration via the serial SMBus interface.

Two free programmable inputs, S0 and S1, can be used to control for each application the most demanding logic control settings (outputs disable to low, outputs 3-state, power down, PLL bypass, etc).

The CDC906 has three power supply pins, VCC, VCCOUT1 and VCCOUT2. VCC is the power supply for the device. It operates from a single 3.3-V supply voltage. VCCOUT1 and VCCOUT2 are the power supply pins for the outputs. VCCOUT1 supplies the outputs Y0 and Y1 and VCCOUT2 supplies the outputs Y2, Y3, Y4, and Y5. Both outputs supplies can be 2.3 V to 3.6 V. At output voltages lower than 3.3 V, the output drive current is limited.

The CDC906 is characterized for operation from 0°C to 70°C.

The CDC906 is one of the smallest and powerful PLL synthesizer / multiplier / divider available today. Despite its small physical outlines, the CDC906 is flexible. It has the capability to produce an almost independent output frequency from a given input frequency.

The input frequency can be derived from a LVCMOS, differential input clock, or a single crystal. The appropriate input waveform can be selected via the SMBus data interface controller.

To achieve an independent output frequency the reference divider M and the feedback divider N for each PLL can be set to values from 1 up to 511 for the M-Divider and from 1 up to 4095 for the N-Divider. The PLL-VCO (voltage controlled oscillator) frequency than is routed to the free programmable output switching matrix to any of the six outputs. The switching matrix includes an additional 7-bit post-divider (1-to-127) and an inverting logic for each output.

The deep M/N divider ratio allows the generation of zero ppm clocks from any reference input frequency (e.g., a 27 MHz).

The CDC906 includes three PLLs of those one supports SSC (spread-spectrum clocking). PLL1, PLL2, and PLL3 are designed for frequencies up to 167 MHz and optimized for zero-ppm applications with wide divider factors.

PLL2 also supports center-spread and down-spread spectrum clocking (SSC). This is a common technique to reduce electro-magnetic interference. Also, the slew-rate controllable (SRC) output edges minimize EMI noise.

Based on the PLL frequency and the divider settings, the internal loop filter components is automatically adjusted to achieve high stability and optimized jitter transfer characteristic of the PLL.

The device provides customized applications. It is preprogrammed with a factory default configuration (see Figure 13) and can be reprogrammed to a different application configuration via the serial SMBus interface.

Two free programmable inputs, S0 and S1, can be used to control for each application the most demanding logic control settings (outputs disable to low, outputs 3-state, power down, PLL bypass, etc).

The CDC906 has three power supply pins, VCC, VCCOUT1 and VCCOUT2. VCC is the power supply for the device. It operates from a single 3.3-V supply voltage. VCCOUT1 and VCCOUT2 are the power supply pins for the outputs. VCCOUT1 supplies the outputs Y0 and Y1 and VCCOUT2 supplies the outputs Y2, Y3, Y4, and Y5. Both outputs supplies can be 2.3 V to 3.6 V. At output voltages lower than 3.3 V, the output drive current is limited.

The CDC906 is characterized for operation from 0°C to 70°C.
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技术文档

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类型 标题 下载最新的英语版本 日期
* 数据表 Programmable 3-PLL Clock Synthesizer / Multiplier / Divider 数据表 (Rev. B) 2008年 2月 11日
应用手册 High Speed Layout Guidelines (Rev. A) 2017年 8月 8日
应用手册 CDCx706/x906 Termination and Signal Integrity Guidelines (Rev. A) 2007年 11月 28日
应用手册 Clock Recommendations for the DM643x EVM 2006年 11月 29日

设计和开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

支持软件

SCAC073 — TI-Pro-Clock Programming Software

支持的产品和硬件

支持的产品和硬件

产品
时钟发生器
CDC706 — 200MHz、LVCMOS、定制编程的 3-PLL 时钟合成器、倍频器和分频器 CDC906 — 167MHz、LVCMOS、定制编程的 3-PLL 时钟合成器、倍频器和分频器 CDCE706 — 300MHz、LVCMOS、可编程 3-PLL 时钟合成器/倍频器/分频器 CDCE906 — 167MHz、LVCMOS、可编程 3-PLL 时钟合成器/倍频器/分频器 CDCE913 — 具有 2.5V 或 3.3V LVCMOS 输出的可编程 1-PLL VCXO 时钟合成器 CDCE925 — 具有 2.5V 或 3.3V LVCMOS 输出的可编程 2-PLL VCXO 时钟合成器 CDCE937 — 具有 2.5V 或 3.3V LVCMOS 输出的可编程 3-PLL VCXO 时钟合成器 CDCE949 — 具有 2.5V 或 3.3V LVCMOS 输出的可编程 4-PLL VCXO 时钟合成器 CDCEL913 — 具有 1.8V LVCMOS 输出的可编程 1-PLL VCXO 时钟合成器 CDCEL925 — 具有 1.8V LVCMOS 输出的可编程 2-PLL VCXO 时钟合成器 CDCEL937 — 具有 1.8V LVCMOS 输出的可编程 3-PLL VCXO 时钟合成器 CDCEL949 — 具有 1.8V LVCMOS 输出的可编程 4-PLL VCXO 时钟合成器
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订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

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