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CDCL6010 状态: ACTIVE

1.8V Eleven Outputs Clock Multiplier Distributor Jitter Cleaner & Buffer

      
         
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数据表

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 CDCL6010
VCC(V)1.8  
Input LevelLVDS  
Output LevelCML  
No. of Outputs10  
Output Frequency(Min)(Mhz)15  
Output Frequency(Max)(Mhz)1250  
Divider Ratio1, 2, 4, 5, 8, 10, 16, 20, 32, 40, 80  
RMS Jitter400fs (1M ~ 20M)  
Operating Frequency Range(Min)(MHz)15  
Operating Frequency Range(Max)(MHz)1250  
Output Skew(ps)+/- 64ps  
Phase Error150ps  
Voltage Range1.7V to 1.9V  
Supply Current(mA)355  
 样片
 库存

产品信息

特性

  • Single 1.8V Supply
  • High-Performance Clock Multiplier, Distributor, Jitter Cleaner, and Buffer With 11 Outputs
  • Low Output Jitter: 400fs RMS
  • Output Group Phase Adjustment
  • Low-Voltage Differential Signaling (LVDS) Input, 100 Single-Ended On-Chip Termination, 15MHz to 1.25GHz Frequency Range
  • One Dedicated Differential CML Output, Straight PLL and Frequency Divider Bypass
  • Two Groups of Five Outputs Each with Independent Frequency Division Ratios; Optional PLL Bypass
  • Fully Integrated Voltage Controlled Oscillator (VCO); Supports Wide Output Frequency Range
  • Output Frequency Derived From VCO Frequency with Divide Ratios of 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, and 80
  • Meets OBSAI RP1 v1.0 Standard and CPRI v2.0 Requirements
  • Meets ANSI TIA/EIA-644-A-2001 LVDS Standard Requirements
  • Integrated LC Oscillator Allows External Bandwidth Adjustment
  • PLL Lock Indication
  • Power Consumption: 640mW Typical
  • Output Enable Control for Each Output
  • SDA/SCL Device Management Interface
  • 48-pin QFN (RGZ) Package
  • Industrial Temperature Range: -40°C to +85°C
  • APPLICATIONS
    • Low Jitter Clocking for High-Speed SERDES
    • Jitter Cleaning of SERDES Reference Clocks for 1G/10G Ethernet, 1X/2X/4X/10X Fibre Channel, PCI Express, Serial ATA, SONET, CPRI, OBSAI, etc.
    • Up to 1-to-11 Clock Buffering and Fan-out

All trademarks are the property of their respective owners

说明

The CDCL6010 is a high-performance, low phase noise clock multiplier, distributor, jitter cleaner, and low skew buffer. It effectively cleans a noisy system clock with a fully-integrated low noise Voltage Controlled Oscillator (VCO) that operates in the 1.2GHz-1.275GHz range. (Note that the LC oscillator oscillates in the 2.4GHz-2.55GHz range. The frequency is predivided by 2 before the post-dividers P0 and P1.)

The output frequency (FOUT) is synchronized to the frequency of the input clock (FIN). The programmable pre-dividers, M and N, and the post-dividers, P0 and P1, give a high flexibility to the ratio of the output frequency to the input frequency:

FOUT = FIN × N/(M × P)

Where:

P (P0, P1) = 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, 80
M = 1, 2, 4, 8
N = 32, 40

provided that:
30MHz < (FIN /M) < 40MHz
1200MHz < (FOUT × P) < 1275MHz

The PLL loop bandwidth is user-selectable by external filter components or by using the internal loop filter. The PLL loop bandwidth and damping factor can be adjusted to meet different system requirements.

The CDCL6010 supports one differential LVDS clock input and a total of 11 differential CML outputs. One output is a straight bypass with no support for jitter cleaning or clock multiplication. The remaining 10 outputs are available in two groups of five outputs each with independent frequency division ratios. Those 10 outputs can be optionally setup to bypass the PLL when no jitter cleaning is needed. The CML outputs are compatible with LVDS receivers if ac-coupled.

With careful observation of the input voltage swing and common-mode voltage limits, the CDCL6010 can support a single-ended clock input as outlined in the Pin Description Table.

The CDCL6010 can operate as a multi-output clock buffer in a PLL bypass mode.

All device settings are programmable through the SDA/SCL, serial two-wire interface.

The phase of one output group relative to the other can be adjusted through the SDA/SCL interface. For post-divide ratios (P0, P1) that are multiples of 5, the total number of phase adjustment steps (n) equals the divide-ratio divided by 5. For post-divide ratios (P0, P1) that are not multiples of 5, the total number of steps (n) is the same as the post-divide ratio. The phase adjustment step () in time units is given as:

= 1/(n × FOUT)

where FOUT is the respective output frequency.

The device operates in a 1.8V supply environment and is characterized for operation from -40°C to +85°C.

The CDCL6010 is available in a 48-pin QFN (RGZ) package.

    

定价/封装/CAD 设计工具/样片

价格（美元）封装CAD 设计工具样片
器件状态温度 (oC)价格（美元） | Quantity封装 | 引脚顶端标记封装数量 | 封装载体符号样片
CDCL6010RGZRACTIVE-40 to 8510.05 | 100uQFN (RGZ) | 48 查看 2500 | LARGE T&R 下载此符号的 CAD 格式采购样片
CDCL6010RGZRG4ACTIVE-40 to 8510.05 | 100uQFN (RGZ) | 48 查看 2500 | LARGE T&R 下载此符号的 CAD 格式采购样片
CDCL6010RGZTACTIVE-40 to 8511.05 | 100uQFN (RGZ) | 48 查看 250 | SMALL T&R 下载此符号的 CAD 格式
CDCL6010RGZTG4ACTIVE-40 to 8511.05 | 100uQFN (RGZ) | 48 查看 250 | SMALL T&R 下载此符号的 CAD 格式请与TI分销商或销售办事处联系申请样片

建议零售价格仅用于预算，以美元为单位，并且价格是浮动的。 若要查询有关批量价格、本地货币价格或交付报价的信息，请与当地德州仪器 (TI) 销售办事处或授权经销商联系。

库存

  TI 库存状态 已报告的分销商库存
CDCL6010RGZR截至 6:42 PM GMT, 2009年 7月 3日截至 6:42 PM GMT, 2009年 7月 3日
 交货周期地区公司库存采购
 20 Weeks无报告
查看经销商		   
CDCL6010RGZRG4截至 6:42 PM GMT, 2009年 7月 3日截至 6:42 PM GMT, 2009年 7月 3日
 交货周期地区公司库存采购
 20 Weeks无报告
查看经销商		   
CDCL6010RGZT截至 6:42 PM GMT, 2009年 7月 3日截至 6:42 PM GMT, 2009年 7月 3日
 交货周期地区公司库存采购
 4 Weeks 中国WPI 165
CDCL6010RGZTG4截至 6:42 PM GMT, 2009年 7月 3日截至 6:42 PM GMT, 2009年 7月 3日
 交货周期地区公司库存采购
 4 Weeks无报告
查看经销商		   

查看中国经销商

**目前尚无法提供交货时间信息。 但是，由于我们的信息每天都会更新，如有疑问，请马上与我们联系。 有关附加信息，请与首选的 TI 授权分销商 联系。

质量与无铅数据

 产品目录DPPM / MTBF / FIT 率
器件环保计划* 铅/焊球涂层MSL 等级/回流焊峰详细信息详细信息
CDCL6010RGZR 符合 RoHS Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR查看查看
CDCL6010RGZRG4 符合 RoHS Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR查看查看
CDCL6010RGZT 符合 RoHS Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR查看查看
CDCL6010RGZTG4 符合 RoHS Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR查看查看

* 计划的环保分级：无铅 (RoHS)、无铅（RoHS 豁免）或绿色环保（RoHS 和无 Sb/Br）- 请单击上表中产品目录明细的“查看”链接，以获得最新供货信息和附加产品目录明细。

如果此时没有在线提供您所请求的信息，则请联系 我们的产品信息中心， 以了解关于此信息可用性的信息。

技术文档

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名称型号 公司 工具/软件类型
CDCL6010EVM 评估模块CDCL6010EVMTexas Instruments开发电路板/EVM

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