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SN74SSQE32882 状态: ACTIVE

符合 JEDEC SSTE32882 的、具有地址奇偶校验的 28 位至 56 位寄存缓冲器

      
         
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 SN74SSQE32882SN74SSQEA32882 
VCC(V)1.425 to 1.575  1.5, 1.35  
Operating Frequency Range(Min)(MHz)300  300  
Operating Frequency Range(Max)(MHz)670  810  
Absolute Jitter (cycle-to-cycle)(ps)40  40  
t(phase error)(Max)(ps)50   
Input LevelSSTL_15  SSTL_15  
No. of Outputs60  60  
Pin/Package176BGA  176BGA  
 样片样片
 库存无库存

产品信息

特性

  • JEDEC SSTE32882 Compliant
  • 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 DIMMs
  • Chip Select Inputs Prevent Data Outputs from Changing State and Minimize System Power Consumption
  • 1.5-V Phase Lock Loop Clock Driver Buffers One Differential Clock Pair (CK and CK) and Distributes to Four Differential Outputs
  • 1.5-V CMOS Inputs
  • Checks Parity on Command and Address (CS-gated) Data Inputs
  • Supports LVCMOS Switching Levels on RESET Input
  • RESET Input:
    • Disables Differential Input Receivers
    • Resets All Registers
    • Forces All Outputs into Pre-defined States
  • Optimal Pinout for DDR3 DIMM PCB Layout
  • Supports Four Chip Selects
  • Single Register Backside Mount Support
  • APPLICATIONS
    • DDR3-Registered DIMMs up to DDR3-1333
    • Single-, Dual- and Quad-Rank RDIMM

All other trademarks are the property of their respective owners

DESCRIPTION/ORDERING INFORMATION

This JEDEC SSTE32882-compliant, 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for operation on DDR3 Registered DIMMs up to DDR3-1333 with VDD of 1.5 V.

All inputs are 1.5-V, CMOS-compatible. All outputs are 1.5-V CMOS drivers optimized to drive DRAM signals on terminated traces in DDR3 RDIMM applications. Clock outputs Yn and Yn and control net outputs DxCKEn, DxCSn, and DxODTn can each be driven with a different strength and skew to optimize signal integrity, compensate for different loading, and balance signal travel speed.

The SN74SSQE32882 has two basic modes of operation associated with the Quad Chip Select Enable (QCSEN) input.

First, when the QCSEN input pin is open or pulled high, the component has two chip select inputs, DCS0 and DCS1, and two copies of each chip select output, QACS0, QACS1, QBCS0 and QBCS1. This mode is the QuadCS disabled mode. Alternatively, when the QCSEN input pin is pulled low, the component has four chip select inputs DCS[3:0], and four chip select outputs, QCS[3:0]. This mode is the QuadCS enabled mode.

When QCSEN is high or floating, the device also supports an operating mode that allows a single device to be mounted on the back side of a DIMM array. This device can then be configured to keep the input bus termination (IBT) feature enabled for all input signals independent of MIRROR. The SN74SSQE32882. operates from a differential clock (CK and CK). Data are registered at the crossing of CK going high and CK going low. This data can either be re-driven to the outputs or used to access internal control registers. Details are covered in the Function Tables (each flip-flop) with QCSEN = low.

Input bus data integrity is protected by a parity function. All address and command input signals are summed; the last bit of the sum is then compared to the parity signal delivered by the system at the PAR_IN input one clock cycle later. If these two values do not match, the device pulls the open drain output ERROUT low. The control signals (DCKE0, DCKE1, DODT0, DODT1, and DCS[n:0]) are not part of this computation.

The SN74SSQE32882 implements different power-saving mechanisms to reduce thermal power dissipation and to support system power-down states. Power consumption is further reduced by disabling unused outputs.

The package design is optimal for high-density DIMMs. By aligning input and output positions towards DIMM finger-signal ordering and SDRAM ballout, the device de-scrambles the DIMM traces and allows low crosstalk designs with low interconnect latency. Edge-controlled outputs reduce ringing and improve signal eye opening at the SDRAM inputs.

    

定价/封装/CAD 设计工具/样片

价格（美元）封装样片
器件状态温度 (oC)价格（美元） | Quantity封装 | 引脚封装数量 | 封装载体样片
SN74SSQE32882ZALRACTIVE0 to 855.90 | 1kuBGA (ZAL) | 176 1000 | LARGE T&R请与TI分销商或销售办事处联系申请样片
SN74SSQE32882ZCJRACTIVE0 to 855.90 | 1kuBGA (ZCJ) | 176 1000 | LARGE T&R请与TI分销商或销售办事处联系申请样片

建议零售价格仅用于预算，以美元为单位，并且价格是浮动的。 若要查询有关批量价格、本地货币价格或交付报价的信息，请与当地德州仪器 (TI) 销售办事处或授权经销商联系。

库存

  TI 库存状态 已报告的分销商库存
SN74SSQE32882ZALR截至 10:13 PM GMT, 2009年 7月 2日截至 10:13 PM GMT, 2009年 7月 2日
 交货周期地区公司库存采购
 10 Weeks无报告
查看经销商		   
SN74SSQE32882ZCJR截至 10:13 PM GMT, 2009年 7月 2日截至 10:13 PM GMT, 2009年 7月 2日
 交货周期地区公司库存采购
 4 Weeks无报告
查看经销商		   

查看中国经销商

**目前尚无法提供交货时间信息。 但是，由于我们的信息每天都会更新，如有疑问，请马上与我们联系。 有关附加信息，请与首选的 TI 授权分销商 联系。

质量与无铅数据

 产品目录DPPM / MTBF / FIT 率
器件环保计划* 铅/焊球涂层MSL 等级/回流焊峰详细信息详细信息
SN74SSQE32882ZALR 符合 RoHS Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR查看查看
SN74SSQE32882ZCJR 符合 RoHS Green (RoHS & no Sb/Br) SNAGAU Level-3-260C-168 HR查看查看

* 计划的环保分级：无铅 (RoHS)、无铅（RoHS 豁免）或绿色环保（RoHS 和无 Sb/Br）- 请单击上表中产品目录明细的“查看”链接，以获得最新供货信息和附加产品目录明细。

如果此时没有在线提供您所请求的信息，则请联系 我们的产品信息中心， 以了解关于此信息可用性的信息。

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