TI 主页 > 半导体 > 处理器平台 > DaVinci™ 数字媒体处理器 > TMS320DM644x DSPs SOC >

TMS320DM6446 状态: ACTIVE

DaVinci 数字媒体片上系统

      
         
此产品变更时通知我


数据表

Download - PDF Icon		 

功能方框图


enlarge 放大

 TMS320DM6446-513TMS320DM6446-594
CPU1 C64x+; 1 ARM9; DaVinci Video  1 C64x+; 1 ARM9; DaVinci Video  
Peak MMACS4104  4752  
RISC Frequency(MHz)256.5  297  
Frequency(MHz)513  594  
On-Chip L1/SRAM112 KB (DSP),40 KB (ARM)  112 KB (DSP),40 KB (ARM)  
On-Chip L2/SRAM64 KB (DSP)  64 KB (DSP)  
ROM16 KB (ARM)  16 KB (ARM)  
EMIF1 16/8-Bit EMIFA,1 32/16-Bit DDR2  1 16/8-Bit EMIFA,1 32/16-Bit DDR2  
External Memory Type SupportedAsync SRAM,DDR2 SDRAM,NAND Flash,SmartMedia/xD  Async SRAM,DDR2 SDRAM,NAND Flash,SmartMedia/xD  
DMA64-Ch EDMA  64-Ch EDMA  
Video Port (Configurable)1 Dedicated Output,1 Dedicated Input  1 Dedicated Output,1 Dedicated Input  
Hardware AcceleratorsResizer,OSD,Previewer,H3A  Resizer,OSD,Previewer,H3A  
Hardware Coprocessor1 VICP - 256.5 MHz  1 VICP - 297 MHz  
EMAC10/100  10/100  
HPI1 16-bit  1 16-bit  
MMC/SD1  1  
DAC4  4  
ATA/CFATA/CF  ATA/CF  
ASP1  1  
I2C1  1  
SPI1  1  
UART3  3  
VLYNQ1  1  
USB1  1  
PWM3  3  
Timers2 64-Bit GP,1 64-Bit WD  2 64-Bit GP,1 64-Bit WD  
Core Supply (Volts)1.2 V  1.2 V  
IO Supply (Volts)1.8 V,3.3 V  1.8 V,3.3 V  
Operating Temperature Range (°C)-40 to 105  0 to 85  
 样片样片
 库存库存

产品信息

特性

  • Get started today with production-ready, easy-to-use audio and video codecs for digital media processors based on DaVinci™ technology. Also available are various O/S Board Support Packages and software updates. All codecs are available for FREE evaluation. REQUEST FREE SOFTWARE!
  • High-Performance Digital Media SoC
    • 513-, 594-MHz C64x+™ Clock Rate
    • 256.5-, 297-MHz ARM926EJ-S™ Clock Rate
    • Eight 32-Bit C64x+ Instructions/Cycle
    • 4752 C64x+ MIPS
    • Fully Software-Compatible With C64x /ARM9™
    • Extended Temperature Devices Available
  • Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Operation
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
    • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 32K-Byte L1P Program RAM/Cache (Direct Mapped)
    • 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative)
    • 64K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • ARM926EJ-S Core
    • Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets
    • DSP Instruction Extensions and Single Cycle MAC
    • ARM® Jazelle® Technology
    • EmbeddedICE-RT™ Logic for Real-Time Debug
  • ARM9 Memory Architecture
    • 16K-Byte Instruction Cache
    • 8K-Byte Data Cache
    • 16K-Byte RAM
    • 8K-Byte ROM
  • Embedded Trace Buffer™ (ETB11™) With 4KB Memory for ARM9 Debug
  • Endianness: Little Endian for ARM and DSP
  • Video Processing Subsystem
    • Front End Provides:
      • CCD and CMOS Imager Interface
      • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
      • Preview Engine for Real-Time Image Processing
      • Glueless Interface to Common Video Decoders
      • Histogram Module
      • Auto-Exposure, Auto-White Balance and Auto-Focus Module
      • Resize Engine
        • Resize Images From 1/4x to 4x
        • Separate Horizontal/Vertical Control
    • Back End Provides:
      • Hardware On-Screen Display (OSD)
      • Four 54-MHz DACs for a Combination of
        • Composite NTSC/PAL Video
        • Luma/Chroma Separate Video (S-video)
        • Component (YPbPr or RGB) Video (Progressive)
      • Digital Output
        • 8-/16-bit YUV or up to 24-Bit RGB
        • HD Resolution
        • Up to 2 Video Windows
  • External Memory Interfaces (EMIFs)
    • 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O)
    • Asynchronous16-Bit Wide EMIF (EMIFA) With 128M-Byte Address Reach
      • Flash Memory Interfaces
        • NOR (8-/16-Bit-Wide Data)
        • NAND (8-/16-Bit-Wide Data)
  • Flash Card Interfaces
    • Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)
    • CompactFlash Controller With True IDE Mode
    • SmartMedia
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit Watch Dog Timer
  • Three UARTs (One with RTS and CTS Flow Control)
  • One Serial Port Interface (SPI) With Two Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Audio Serial Port (ASP)
    • I2S
    • AC97 Audio Codec Interface
    • Standard Voice Codec Interface (AIC12)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Media Independent Interface (MII)
  • VLYNQ™ Interface (FPGA Interface)
  • Host Port Interface (HPI) with 16-Bit Multiplexed Address/Data
  • USB Port With Integrated 2.0 PHY
    • USB 2.0 High-/Full-Speed (480-Mbps) Client
    • USB 2.0 High-/Full-/Low-Speed Host (Mini-Host, Supporting One External Device)
  • Three Pulse Width Modulator (PWM) Outputs
  • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash or UART
  • ATA/ATAPI I/F (ATA/ATAPI-6 Specification)
  • Individual Power-Saving Modes for ARM/DSP
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • Up to 71 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • 361-Pin Pb-Free BGA Package (ZWT Suffix), 0.8-mm Ball Pitch
  • 0.09-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.2-V Internal
  • Applications:
    • Digital Media
    • Networked Media Encode/Decode
    • Video Imaging

All trademarks are the property of their respective owners.

说明

The TMS320DM6446 (also referenced as DM6446) leverages TI's Davinci™ technology to meet the networked media encode and decode application processing needs of next-generation embedded devices.

The DM6446 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the DM6446 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C64x+ DSP core and an ARM926EJ-S MPU core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core incorporates:

  • A coprocessor 15 (CP15) and protection module
  • Data and program Memory Management Units (MMUs) with table look-aside buffers.
  • Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).

The TMS320C64x+™ DSPs are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. It is based on an enhanced version of the second-generation high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSP cores an excellent choice for digital media applications. The C64x is a code-compatible member of the C6000™ DSP platform. The TMS320C64x+ DSP is an enhancement of the C64x+ DSP with added functionality and an expanded instruction set.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 4752 million instructions per second (MIPS) at a clock rate of 594 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2376 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4752 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The DM6446 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6446 core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 512K-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: 2 configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; an inter-integrated circuit (I2C) Bus interface; one audio serial port (ASP); 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; up to 71-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; and 2 external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The DM6446 device includes a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals: 1 Video Processing Front-End (VPFE) input used for video capture, 1 Video Processing Back-End (VPBE) output with imaging co-processor (VICP) used for display.

The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC), a Preview Engine (Previewer), Histogram Module, Auto-Exposure/White Balance/Focus Module (H3A), and Resizer. The CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices (CCDs). The Previewer is a real-time image processing engine that takes raw imager data from a CMOS sensor or CCD and converts from an RGB Bayer Pattern to YUV422. The Histogram and H3A modules provide statistical information on the raw color data for use by the DM6446. The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024.

The Video Processing Back-End (VPBE) is comprised of an On-Screen Display Engine (OSD) and a Video Encoder (VENC). The OSD engine is capable of handling 2 separate video windows and 2 separate OSD windows. Other configurations include 2 video windows, 1 OSD window, and 1 attribute window allowing up to 8 levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz, providing a means for composite NTSC/PAL video, S-Video, and/or Component video output. The VENC also provides up to 24 bits of digital output to interface to RGB888 devices. The digital output is capable of 8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM644X MPU core processor and the network. The DM6446 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the MPU, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the MPU, allowing the MPU to poll the link status of the device without continuously performing costly MDIO accesses.

The HPI, I2C, SPI, USB2.0, and VLYNQ ports allow DM6446 to easily control peripheral devices and/or communicate with host processors. The DM6446 also provides multimedia card support, MMC/SD, with SDIO support.

The DM6446 also includes a Video/Imaging Co-processor (VICP) to offload many video and imaging processing tasks from the DSP core, making more DSP MIPS available for common video and imaging algorithms. For more information on the VICP enhanced codecs, such as H.264 and MPEG4, please contact your nearest TI sales representative.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The DM6446 has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code

    

定价/封装/CAD 设计工具/样片

价格（美元）封装CAD 设计工具样片
器件状态温度 (oC)价格（美元） | Quantity封装 | 引脚封装数量 | 封装载体符号尺寸样片
TMS320DM6446AZWTACTIVE0 to 8539.35 | 100uNFBGA (ZWT) | 361 90  采购样片
TMS320DM6446AZWTAACTIVE-40 to 10539.35 | 100uNFBGA (ZWT) | 361 90  采购样片
TMS320DM6446ZWTOBSOLETE0 to 85 NFBGA (ZWT) | 361   下载此符号的 CAD 格式 下载此尺寸的 CAD 格式无

建议零售价格仅用于预算，以美元为单位，并且价格是浮动的。 若要查询有关批量价格、本地货币价格或交付报价的信息，请与当地德州仪器 (TI) 销售办事处或授权经销商联系。

库存

  TI 库存状态 已报告的分销商库存
TMS320DM6446AZWT截至 4:58 PM GMT, 2009年 7月 3日截至 4:58 PM GMT, 2009年 7月 3日
 交货周期地区公司库存采购
 6 Weeks无报告
查看经销商		   
TMS320DM6446AZWTA截至 4:58 PM GMT, 2009年 7月 3日截至 4:58 PM GMT, 2009年 7月 3日
 交货周期地区公司库存采购
 5 Weeks无报告
查看经销商		   
TMS320DM6446ZWT截至 4:58 PM GMT, 2009年 7月 3日截至 4:58 PM GMT, 2009年 7月 3日
 交货周期地区公司库存采购
 16 Weeks 中国WPI 101

查看中国经销商

**目前尚无法提供交货时间信息。 但是，由于我们的信息每天都会更新，如有疑问，请马上与我们联系。 有关附加信息，请与首选的 TI 授权分销商 联系。

质量与无铅数据

 产品目录DPPM / MTBF / FIT 率
器件环保计划* 铅/焊球涂层MSL 等级/回流焊峰详细信息详细信息
TMS320DM6446AZWT 符合 RoHS Pb-Free (RoHS) Call TI Level-3-260C-168 HR查看查看
TMS320DM6446AZWTA 符合 RoHS Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR查看查看
TMS320DM6446ZWT  Pb-Free (RoHS) Call TI Level-3-260C-168 HR查看查看

* 计划的环保分级：无铅 (RoHS)、无铅（RoHS 豁免）或绿色环保（RoHS 和无 Sb/Br）- 请单击上表中产品目录明细的“查看”链接，以获得最新供货信息和附加产品目录明细。

如果此时没有在线提供您所请求的信息，则请联系 我们的产品信息中心， 以了解关于此信息可用性的信息。

技术文档

TMS320DM6446 最新技术文档 Help

数据表

应用手册

查看 TMS320DM644x DSPs SOC 的应用手册

用户指南

查看 TMS320DM644x DSPs SOC 的用户指南

解决方案指南

模型

查看 TMS320DM644x DSPs SOC 的模拟模型

白皮书

View White Papers for TMS320DM644x DSPs SOC

勘误表

更多文献资料

查看 TMS320DM644x DSPs SOC 的更多文献资料

工具与软件

名称型号 公司 工具/软件类型
Code Composer Studio IDECCSTUDIOTexas InstrumentsCode Composer Studio(TM) IDE
XDS510 类仿真器XDS510Texas Instruments仿真器/分析仪
XDS560 类高速仿真器XDS560Texas Instruments仿真器/分析仪
自适应时钟 JTAG 仿真适配器TMDSADPTexas Instruments仿真器/分析仪
Blackhawk™ LAN560 JTAG EmulatorBlackhawk仿真器/分析仪
Blackhawk™ PCI560 JTAG Emulator for TI DSPsBlackhawk仿真器/分析仪
Blackhawk™ USB560 JTAG EmulatorBlackhawk仿真器/分析仪
Blackhawk™ USB560BP JTAG EmulatorBlackhawk仿真器/分析仪
XDS510USB PLUS JTAG EmulatorSpectrum Digital, Inc.仿真器/分析仪
DaVinci EVM Prototyping Circuit BoardLink Research子卡
DM6437 数字视频开发平台TMDSVDP6437Texas Instruments开发平台
基于 DaVinci™ 技术的数字视频软件产品包 (DVSPB)TMDSDVSPBA9Texas Instruments开发平台
DM6446 数字视频评估模块TMDSEVM6446Texas Instruments开发电路板/EVM
MPEG-4 视频解码器TMDMPEG4D Texas Instruments 算法/ 解码器 
Windows CE EVM 软件（OS 和 BSP）S1SDKWCE Texas Instruments DSP/BIOS 实时内核 
H.264 视频编码器TMDH264E Texas Instruments 算法/ 解码器 
JPEG 成像解码器TMDJPEGD Texas Instruments 算法/ 解码器 
MPEG-2 视频编码器TMDMPEG2E Texas Instruments 算法/ 解码器 
AAC HE 和 LC 音频编码器TMDAACE Texas Instruments 算法/ 解码器 
用于达芬奇器件的 Linux 数字视频软件开发套件 (DVSDK)LINUXDVSDK-DV Texas Instruments DSP/BIOS 实时内核 
VICP 信号处理库SPRC831 Texas Instruments 信号处理库 
MPEG-2 视频解码器TMDMPEG2D Texas Instruments 算法/ 解码器 
MP3 音频解码器TMDMP3D Texas Instruments 算法/ 解码器 
MPEG-4 视频编码器TMDMPEG4E Texas Instruments 算法/ 解码器 
QNX Neutrino RTOS QNX Software Systems DSP/BIOS 实时内核 
TMS320C62x/TMS320C64x FastRTS 库SPRC122 Texas Instruments 信号处理库 
C64x+IMGLIBSPRC264 Texas Instruments 信号处理库 
H.264 视频解码器TMDH264D Texas Instruments 算法/ 解码器 
MP3 音频编码器TMDMP3E Texas Instruments 算法/ 解码器 
eXpressDSP 算法标准 – xDAIS 开发者套件和 xDMTMDXDAISXDM Texas Instruments 算法/ 解码器 
AAC HE 和 LC 音频解码器TMDAACD Texas Instruments 算法/ 解码器 
JPEG 成像编码器TMDJPEGE Texas Instruments 算法/ 解码器 
驱动程序/平台支持包 (PSP)SUPPORTPKG Texas Instruments 驱动程序/ IO/ 控制 软件 
多媒体框架产品 (MFP) - 编解码引擎和 xDAIS 框架组件TMDMFP Texas Instruments 框架软件 

型号 名称 产品系列 注释
TVP5150AM1   具有强大可靠的同步检测器的超低功耗 NTSC/PAL/SECAM 视频解码器   VIDEO AND IMAGING - VIDEO ENCODERS / DECODERS   Complementary Analog Part    
TPS40200   宽输入非同步降压 DC/DC 控制器   NON-ISOLATED SWITCHING DC/DC REGULATORS - DC/DC CONTROLLERS (EXTERNAL SWITCH)      
TPS65020   具有 3DC/DC、3 LDO、I2C 接口和动态电压缩放的 6 通道电源管理 IC   POWER MANAGEMENT MULTI-CHANNEL IC (PMIC) SOLUTIONS - PMIC SOLUTIONS WITH AND WITHOUT BATTERY CHARGER      
TPS62020   可调节 600mA 95% 效率步降转换器，静态电流 18uA，采用 MSOP-10 封装   DC/DC CONVERTERS (INTEGRATED SWITCH) - STEP-DOWN REGULATORS      
TPS65040   Clock and Power Management IC for RF System   POWER MANAGEMENT MULTI-CHANNEL IC (PMIC) SOLUTIONS - PMIC SOLUTIONS WITH AND WITHOUT BATTERY CHARGER      
TPS62220   采用小型 SOT-23 封装的可调节 400mA、95% 高效步降控制器，15uA   DC/DC CONVERTERS (INTEGRATED SWITCH) - STEP-DOWN REGULATORS      
TPS62111   采用 QFN-16 封装的 3.3V 1.5A 输出 17V 输入的步降转换器   DC/DC CONVERTERS (INTEGRATED SWITCH) - STEP-DOWN REGULATORS      
TPS73701   单路输出 LDO、1A、可调节 （1.2 至 5.0V）反向电流保护   LINEAR REGULATORS - SINGLE CHANNEL LDO      
TPS78633   单输出 LDO、1.5A、固定电压 (3.3V)、低噪声、高 PSRR   LINEAR REGULATORS - SINGLE CHANNEL LDO      
TPS74401   单输出 LDO、3.0A、可调节电压（0.8 至 3.3V）、快速瞬态响应、可编程软启动   LINEAR REGULATORS - SINGLE CHANNEL LDO      

相关应用产品

所有应用产品

支持和社区

其它支持资源



Click Here