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TMS320VC5510A 状态: ACTIVE

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 TMS320VC5510A-160TMS320VC5510A-200
CPU1 C55x  1 C55x  
Peak MMACS320  400  
Frequency(MHz)160  200  
RAM320 KB  320 KB  
ROM32 KB  32 KB  
On-Chip L1/SRAM24 KB  24 KB  
EMIF1 32-Bit  1 32-Bit  
External Memory Type SupportedAsync SRAM,SBSRAM,SDRAM  Async SRAM,SBSRAM,SDRAM  
DMA1 6-Ch Int/Ext DMA  1 6-Ch Int/Ext DMA  
HPI1 16-Bit EHPI  1 16-Bit EHPI  
McBSP3  3  
Timers2 16-Bit GP  2 16-Bit GP  
Boot Loader AvailableYES  YES  
Hardware AcceleratorsImage/Video Extension  Image/Video Extension  
Core Supply (Volts)1.6 V  1.6 V  
IO Supply (Volts)3.3 V  3.3 V  
Operating Temperature Range (°C)-40 to 85,0 to 85  -40 to 85,0 to 85  
RatingCatalog  Catalog  
 样片样片
 库存库存

产品信息

特性

  • High-Performance, Low-Power, Fixed-Point TMS320C55x™; Digital Signal Processor (DSP)
    • 6.25-/5-ns Instruction Cycle Time
    • 160-/200-MHz Clock Rate
    • One/Two Instructions Executed per Cycle
    • Dual Multipliers (Up to 400 Million Multiply-Accumulates Per Second (MMACS))
    • Two Arithmetic/Logic Units
    • One Internal Program Bus
    • Three Internal Data/Operand Read Buses
    • Two Internal Data/Operand Write Buses
  • Instruction Cache (24K Bytes)
  • 160K x 16-Bit On-Chip RAM Composed of:
    • Eight Blocks of 4K × 16-Bit Dual-Access RAM (DARAM) (64K Bytes)
    • 32 Blocks of 4K × 16-Bit Single-Access RAM (SARAM)(256K Bytes)
  • 16K × 16-Bit On-Chip ROM (32K Bytes)
  • 8M × 16-Bit Maximum Addressable External Memory Space
  • 32-Bit External Memory Interface (EMIF) With Glueless Interface to:
    • Asynchronous Static RAM (SRAM)
    • Asynchronous EPROM
    • Synchronous DRAM (SDRAM)
    • Synchronous Burst SRAM (SBSRAM)
  • Programmable Low-Power Control of Six Device Functional Domains
  • On-Chip Peripherals
    • Two 20-Bit Timers
    • Six-Channel Direct Memory Access (DMA) Controller
    • Three Multichannel Buffered Serial Ports (McBSPs)
    • 16-Bit Parallel Enhanced Host-Port Interface (EHPI)
    • Programmable Digital Phase-Locked Loop (DPLL) Clock Generator
    • Eight General-Purpose I/O (GPIO) Pins and Dedicated General-Purpose Output (XF)
  • On-Chip Scan-Based Emulation Logic
  • IEEE Std 1149.1 (JTAG) Boundary Scan Logic
  • 240-Terminal MicroStar BGA™; (Ball Grid Array) (GGW Suffix)
  • 240-Terminal MicroStar BGA™; (Ball Grid Array) (ZGW Suffix) [Lead-Free]
  • 3.3-V I/O Supply Voltage
  • 1.6-V Core Supply Voltage

TMS320C55x and MicroStar BGA are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
C55x, eXpressDSP, Code Composer Studio, DSP/BIOS, TMS320, RTDX, and XDS510 are trademarks of Texas Instruments.

说明

The TMS320VC5510/5510A (5510/5510A) fixed-point digital signal processors (DSPs) are based on the TMS320C55x DSP generation CPU processor core. The C55x™;DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the address unit (AU) and data unit (DU) of the C55x CPU.

The C55x™; DSP generation supports a variable byte width instruction set for improved code density. The instruction unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the program unit (PU). The program unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions. The 5510/5510A also includes a 24K-byte instruction cache to minimize external memory accesses, improving data throughput and conserving system power.

The 5510/5510A peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM and synchronous burst SRAM. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The enhanced host-port interface (EHPI) is a 16-bit parallel interface used to provide host processor access to internal memory on the 5510/5510A. The EHPI can be configured in either multiplexed or non-multiplexed mode to provide glueless interface to a wider variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention, providing DMA throughput of up to two 16-bit words per cycle. Two general-purpose timers, eight general-purpose I/O (GPIO) pins, and digital phase-locked loop (DPLL) clock generation are also included.

The 5510/5510A is supported by the industry’s leading eXpressDSP™; software environment including the Code Composer Studio™; integrated development environment, DSP/BIOS™; software kernel foundation, the TMS320™; DSP Algorithm Standard, and the industry’s largest third-party network. Code Composer Studio features code generation tools including a C-Compiler, Visual Linker, simulator, Real-Time Data Exchange (RTDX™;), XDS510™; emulation device drivers, and Chip Support Libraries (CSL). DSP/BIOS is a scalable real-time software foundation available for no cost to users of Texas Instruments’ DSP products providing a pre-emptive task scheduler and real-time analysis capabilities with very low memory and megahertz overhead. The TMS320 DSP Algorithm Standard is a specification of coding conventions allowing fast integration of algorithms from different teams, sites, or third parties into the application framework. Texas Instruments’ extensive DSP third-party network of over 400 providers brings focused competencies and complete solutions to customers.

Texas Instruments (TI) has also developed foundation software available for the 5510/5510A. The C55x DSP Library (DSPLIB) features over 50 C-callable software kernels (FIR/IIR filters, Fast Fourier Transforms (FFTs), and various computational functions). The DSP Image/Video Processing Library (IMGLIB) contains over 20 software kernels highly optimized for C55x DSPs and is compiled with the latest revision of the C55x DSP code generation tools. These imaging functions support a wide range of applications that include compression, video processing, machine vision, and medical imaging.

The TMS320C55x DSP core was created with an open architecture that allows the addition of application-specific hardware to boost performance on specific algorithms. The hardware extensions on the 5510/5510A strike the perfect balance of fixed function performance with programmable flexibility, while achieving low-power consumption, and cost that traditionally has been difficult to find in the video-processor market. The extensions allow the 5510/5510A to deliver exceptional video codec performance with more than half its bandwidth available for performing additional functions such as color space conversion, user-interface operations, security, TCP/IP, voice recognition, and text-to-speech conversion. As a result, a single 5510/5510A DSP can power most portable digital video applications with processing headroom to spare. For more information, see the TMS320C55x Hardware Extensions for Image/Video Applications Programmer’s Reference (literature number SPRU098). For more information on using the the DSP Image Processing Library, see the TMS320C55x Image/Video Processing Library Programmer’s Reference (literature number SPRU037).

    

定价/封装/CAD 设计工具/样片

价格（美元）封装CAD 设计工具样片
器件状态价格（美元） | Quantity封装 | 引脚封装数量 | 封装载体符号尺寸样片
TMS320VC5510AGGW1ACTIVE15.90 | 100uBGA MICROSTAR (GGW) | 240 126 下载此符号的 CAD 格式 下载此尺寸的 CAD 格式采购样片
TMS320VC5510AGGW2ACTIVE18.60 | 100uBGA MICROSTAR (GGW) | 240 126 下载此符号的 CAD 格式 下载此尺寸的 CAD 格式
TMS320VC5510AGGWA1ACTIVE19.10 | 100uBGA MICROSTAR (GGW) | 240 126 下载此符号的 CAD 格式 下载此尺寸的 CAD 格式采购样片
TMS320VC5510AGGWA2ACTIVE21.95 | 100uBGA MICROSTAR (GGW) | 240 126 下载此符号的 CAD 格式 下载此尺寸的 CAD 格式采购样片
TMS320VC5510AZGW1ACTIVE15.90 | 100uBGA MICROSTAR (ZGW) | 240 126 下载此符号的 CAD 格式 下载此尺寸的 CAD 格式采购样片
TMS320VC5510AZGW2ACTIVE18.60 | 100uBGA MICROSTAR (ZGW) | 240 126 下载此符号的 CAD 格式 下载此尺寸的 CAD 格式采购样片
TMS320VC5510AZGWA1ACTIVE19.10 | 100uBGA MICROSTAR (ZGW) | 240 126 下载此符号的 CAD 格式 下载此尺寸的 CAD 格式采购样片
TMS320VC5510AZGWA2ACTIVE21.80 | 100uBGA MICROSTAR (ZGW) | 240 126 下载此符号的 CAD 格式 下载此尺寸的 CAD 格式采购样片

建议零售价格仅用于预算，以美元为单位，并且价格是浮动的。 若要查询有关批量价格、本地货币价格或交付报价的信息，请与当地德州仪器 (TI) 销售办事处或授权经销商联系。

库存

  TI 库存状态 已报告的分销商库存
TMS320VC5510AGGW1截至 4:57 PM GMT, 2009年 7月 3日截至 4:57 PM GMT, 2009年 7月 3日
 交货周期地区公司库存采购
 8 Weeks无报告
查看经销商		   
TMS320VC5510AGGW2截至 4:57 PM GMT, 2009年 7月 3日截至 4:57 PM GMT, 2009年 7月 3日
 交货周期地区公司库存采购
 8 Weeks 中国WPI 140
TMS320VC5510AGGWA1截至 4:57 PM GMT, 2009年 7月 3日截至 4:57 PM GMT, 2009年 7月 3日
 交货周期地区公司库存采购
 8 Weeks无报告
查看经销商		   
TMS320VC5510AGGWA2截至 4:57 PM GMT, 2009年 7月 3日截至 4:57 PM GMT, 2009年 7月 3日
 交货周期地区公司库存采购
 7 Weeks无报告
查看经销商		   
TMS320VC5510AZGW1截至 4:57 PM GMT, 2009年 7月 3日截至 4:57 PM GMT, 2009年 7月 3日
 交货周期地区公司库存采购
 8 Weeks无报告
查看经销商		   
TMS320VC5510AZGW2截至 4:57 PM GMT, 2009年 7月 3日截至 4:57 PM GMT, 2009年 7月 3日
 交货周期地区公司库存采购
 8 Weeks无报告
查看经销商		   
TMS320VC5510AZGWA1截至 4:57 PM GMT, 2009年 7月 3日截至 4:57 PM GMT, 2009年 7月 3日
 交货周期地区公司库存采购
 8 Weeks无报告
查看经销商		   
TMS320VC5510AZGWA2截至 4:57 PM GMT, 2009年 7月 3日截至 4:57 PM GMT, 2009年 7月 3日
 交货周期地区公司库存采购
 8 Weeks无报告
查看经销商		   

查看中国经销商

**目前尚无法提供交货时间信息。 但是，由于我们的信息每天都会更新，如有疑问，请马上与我们联系。 有关附加信息，请与首选的 TI 授权分销商 联系。

质量与无铅数据

 产品目录DPPM / MTBF / FIT 率
器件环保计划* 铅/焊球涂层MSL 等级/回流焊峰详细信息详细信息
TMS320VC5510AGGW1  TBD SNPB Level-3-220C-168 HR查看查看
TMS320VC5510AGGW2  TBD SNPB Level-3-220C-168 HR查看查看
TMS320VC5510AGGWA1  TBD SNPB Level-3-220C-168 HR查看查看
TMS320VC5510AGGWA2  TBD SNPB Level-3-220C-168 HR查看查看
TMS320VC5510AZGW1 符合 RoHS Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR查看查看
TMS320VC5510AZGW2 符合 RoHS Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR查看查看
TMS320VC5510AZGWA1 符合 RoHS Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR查看查看
TMS320VC5510AZGWA2 符合 RoHS Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR查看查看

* 计划的环保分级：无铅 (RoHS)、无铅（RoHS 豁免）或绿色环保（RoHS 和无 Sb/Br）- 请单击上表中产品目录明细的“查看”链接，以获得最新供货信息和附加产品目录明细。

如果此时没有在线提供您所请求的信息，则请联系 我们的产品信息中心， 以了解关于此信息可用性的信息。

技术文档

TMS320VC5510A 最新技术文档 Help

数据表

应用手册

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用户指南

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模型

查看 TMS320C55x 低功耗 DSP 的模拟模型

勘误表

工具与软件

名称型号 公司 工具/软件类型
Code Composer Studio IDECCSTUDIOTexas InstrumentsCode Composer Studio(TM) IDE
Code Composer Studio IDE 订购服务CCSTUDIOSUBSCRIPTIONSTexas InstrumentsCode Composer Studio(TM) IDE
XDS510 类仿真器XDS510Texas Instruments仿真器/分析仪
XDS560 类高速仿真器XDS560Texas Instruments仿真器/分析仪
Blackhawk™ LAN560 JTAG EmulatorBlackhawk仿真器/分析仪
Blackhawk™ PCI560 JTAG Emulator for TI DSPsBlackhawk仿真器/分析仪
Blackhawk™ USB560BP JTAG EmulatorBlackhawk仿真器/分析仪
JTAGjet USB 2.0 Emulator for TMS320Signum Systems仿真器/分析仪
XDS510PP PLUS JTAG EmulatorSpectrum Digital, Inc.仿真器/分析仪
XDS510USB JTAG EmulatorSpectrum Digital, Inc.仿真器/分析仪
XDS510USB PLUS JTAG EmulatorSpectrum Digital, Inc.仿真器/分析仪
TMS320VC5509A DSP 入门套件 (DSK)TMDSDSK5509Texas Instruments入门套件
TMS320VC5510 DSP 入门套件 (DSK)TMDSDSK5510Texas Instruments入门套件
TMS320VC5505 DSP 评估模块TMDXEVM5505Texas Instruments开发电路板/EVM
Q-VGA LCD Module for OMAP5912Mistral Solutions Pvt. Ltd开发电路板/EVM
OMAP OSK 闪存恢复实用程序TMDSSDSFRUTexas Instruments闪存工具
TMS320C55x DSP 库SPRC100 Texas Instruments 信号处理库 
TMS320C55x 芯片支持库SPRC133 Texas Instruments 应用软件 
TMS320C55x 图像库SPRC101 Texas Instruments 信号处理库 
DSP/BIOS II 实时内核DSPBIOS Texas Instruments DSP/BIOS 实时内核 

型号 名称 产品系列 注释
AFE1230   G.SHDSL 模拟前端   DSL ANALOG FRONT ENDS - DSL CODECS      

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