UC2825A-Q1 状态:ACTIVE

汽车类高速 PWM 控制器

      
         
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数据表

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  • High-Speed PWM Controller (uc2825a-q1.pdf, 451 KB)
    2007年 9月 27日 下载(英文內容)

 UC2825A-Q1
TopologyBoost, Flyback, Forward, Full-Bridge, Half-Bridge, Push-Pull  
Control MethodCurrent Mode  
Duty Cycle(Max)(%)50  
PWM Outputs(#)2  
Frequency(Max)(kHz)1000  
UVLO Thresholds On/Off(V)9.2/8.4  
Pin/Package16SOIC  
 样片
 无库存

产品信息

特性

  • Qualified for Automotive Applications
  • Improved Version of the UC3825 PWM
  • Compatible With Voltage-Mode or Current-Mode Control Methods
  • Practical Operation at Switching Frequencies to 1 MHz
  • 50-ns Propagation Delay to Output
  • High-Current Dual Totem-Pole Outputs: 2 A (Peak)
  • Trimmed Oscillator Discharge Current
  • Low 100-µA Startup Current
  • Pulse-by-Pulse Current-Limiting Comparator
  • Latched Overcurrent Comparator With Full-Cycle Restart

说明

The UC2825A pulse-width modulation (PWM) controller is an improved versions of the standard UC3825. Performance enhancements have been made to several of the circuit blocks. Error amplifier gain bandwidth product is 12 MHz, while input offset voltage is 2 mV. Current limit threshold is specified to a tolerance of 5%. Oscillator discharge current is specified at 10 mA for accurate dead-time control. Frequency accuracy is improved to 6%. Startup supply current, typically 100 µA, is ideal for off-line applications. The output drivers are redesigned to actively sink current during undervoltage lockout (UVLO) at no expense to the startup current specification. In addition, each output is capable of 2-A peak currents during transitions.

Functional improvements have also been implemented. The shutdown comparator is now a high-speed overcurrent comparator with a threshold of 1.2 V. The overcurrent comparator sets a latch that ensures full discharge of the soft-start capacitor before allowing a restart. While the fault latch is set, the outputs are in the low state. In the event of continuous faults, the soft-start capacitor is fully charged before discharge to insure that the fault frequency does not exceed the designed soft start period. The CLOCK pin has become CLK/LEB. This pin combines the functions of clock output and leading edge blanking adjustment and has been buffered for easier interfacing.

The UC2825A has dual alternating outputs and the same pin configuration of the UC3825. "A" version parts have UVLO thresholds identical to the original UC3825.

See the application report, The UC3823A,B and UC3825A,B Enhanced Generation of PWM Controllers (SLUA125) for detailed technical and application information.

    

定价/封装/CAD 设计工具/样片

价格(美元)封装CAD 设计工具样片
器件状态温度 (oC)价格(美元) | Quantity封装 | 引脚顶端标记封装数量 | 封装载体符号尺寸样片
UC2825AQDWRQ1ACTIVE-40 to 1253.90 | 100uSOIC (DW) | 16 查看 2000 下载此符号的 CAD 格式 下载此尺寸的 CAD 格式采购样片

建议零售价格仅用于预算,以美元为单位,并且价格是浮动的。
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质量与无铅数据

 产品目录DPPM / MTBF / FIT 率
器件环保计划* 铅/焊球涂层MSL 等级/回流焊峰详细信息详细信息
UC2825AQDWRQ1 符合 RoHS Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR查看查看

* 计划的环保分级:无铅 (RoHS)、无铅(RoHS 豁免)或绿色环保(RoHS 和无 Sb/Br)- 请单击上表中产品目录明细的“查看”链接,以获得最新供货信息和附加产品目录明细。

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技术文档

数据表

  • High-Speed PWM Controller (uc2825a-q1.pdf, 451 KB)
    2007年 9月 27日 下载(英文內容)

应用手册

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