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产品信息特性
OHCI-Lynx is a trademark of Texas Instruments. 说明
The Texas Instruments XIO2213A is a PCI Express to PCI translation bridge where the PCI bus interface is internally connected to a 1394b open host controller link-layer controller with a three-port 1394b PHY. The PCI-Express to PCI translation bridge is fully compatible with the PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0. Also, the bridge supports the standard PCI-to-PCI bridge programming model. The 1394b OHCI controller function is fully compatible with IEEE Standard 1394b and the latest 1394 Open Host Controller Interface (OHCI) Specification. The XIO2213A simultaneously supports up to four posted write transactions, four non-posted transactions, and four completion transactions pending in each direction at any time. Each posted write data queue and completion data queue can store up to 8K bytes of data. The non-posted data queues can store up to 128 bytes of data. The PCI Express interface supports a x1 link operating at full 250 MB/s packet throughput in each direction simultaneously. Also, the bridge supports the advanced error reporting capability including ECRC as defined in the PCI Express Base Specification, Revision 1.1. Supplemental firmware or software is required to fully utilize both of these features. Robust pipeline architecture is implemented to minimize system latency. If parity errors are detected, then packet poisoning is supported for both upstream and downstream operations. The PCIe Power management (PM) features include active state link PM, PME mechanisms, and all conventional PCI D-states. If the active state link PM is enabled, then the link automatically saves power when idle using the L0s and L1 states. PM active state NAK, PM PME, and PME-to-ACK messages are supported. The bridge is compliant with the latest PCI Bus Power Management Specification and provides several low-power modes, which enable the host power system to further reduce power consumption Eight general-purpose inputs and outputs (GPIOs), configured through accesses to the PCI Express configuration space, allow for further system control and customization. Deep FIFOs are provided to buffer 1394 data and accommodate large host bus latencies. The device provides physical write posting and a highly tuned physical data path for SBP-2 performance. The device is capable of transferring data between the PCI Express bus and the 1394 bus at 100M bits/s, 200M bits/s, 400M bits/s, and 800M bits/s. The device provides three 1394 ports that have separate cable bias (TPBIAS). As required by the 1394 Open Host Controller Interface Specification, internal control registers are memory-mapped and nonprefetchable. This configuration header is accessed through configuration cycles specified by PCI Express, and it provides plug-and-play (PnP) compatibility. The PHY-layer provides the digital and analog transceiver functions needed to implement a three-port node in a cable-based 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. An optional external 2-wire serial EEPROM interface is provided to load the global unique ID for the 1394 fabric. The XIO2213A requires an external 98.304-MHz crystal oscillator to generate a reference clock. The external clock drives an internal phase-locked loop (PLL), which generates the required reference signal. This reference signal provides the clock signals that control transmission of the outbound encoded information. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL. Data bits to be transmitted through the cable ports are latched internally, combined serially, encoded, and transmitted at 98.304, 196.608, 393.216, 491.52, or 983.04 Mbps (referred to as S100, S200, S400, S400B, or S800 speed, respectively) as the outbound information stream. To ensure that the XIO2213A conforms to the IEEE Std 1394b-2002 standard, the BMODE terminal must be asserted. The BMODE terminal does not select the cable-interface mode of operation. The BMODE terminal selects the internal PHY section-LLC section interface mode of operation and affects the arbitration modes on the cable. BMODE must be pulled high during normal operation. Three package terminals are used as inputs to set the default value for three configuration status bits in the self-ID packet. They can be pulled high through a 1-Ω resistor or hardwired low as a function of the equipment design. The PC0, PC1, and PC2 terminals indicate the default power class status for the node (the need for power from the cable or the ability to supply power to the cable). The contender bit in the PHY register set indicates that the node is a contender either for the isochronous resource manager (IRM) or for the bus manager (BM). On the XIO2213A, this bit can only be set by a write to the PHY register set. If a node is to be a contender for IRM or BM, the node software must set this bit in the PHY register set. |
| 价格（美元） | 封装 | 样片 | ||||
| 器件 | 状态 | 温度 (oC) | 价格（美元） | Quantity | 封装 | 引脚 | 封装数量 | 封装载体 | 样片 |
| XIO2213AZAY | ACTIVE | 0 to 70 | 8.70 | 1ku | NFBGA (ZAY) | 167 | 160 | JEDEC TRAY (5+1) | 请与TI分销商或销售办事处联系申请样片 |
建议零售价格仅用于预算，以美元为单位，并且价格是浮动的。 若要查询有关批量价格、本地货币价格或交付报价的信息，请与当地德州仪器 (TI) 销售办事处或授权经销商联系。
| TI 库存状态 | 已报告的分销商库存 | |||||||
| XIO2213AZAY | 截至 4:14 PM GMT, 2009年 7月 3日 | 截至 4:14 PM GMT, 2009年 7月 3日 | ||||||
| 交货周期 | 地区 | 公司 | 库存 | 采购 | ||||
| 6 Weeks | 中国 | WPI | 60 | |||||
| 查看中国经销商 | ||||||||
**目前尚无法提供交货时间信息。 但是，由于我们的信息每天都会更新，如有疑问，请马上与我们联系。 有关附加信息，请与首选的 TI 授权分销商 联系。
| 产品目录 | DPPM / MTBF / FIT 率 | ||||
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 详细信息 | 详细信息 |
XIO2213AZAY  | Green (RoHS & no Sb/Br) | SNAGCU | Level-3-260C-168 HR | 查看 | 查看 |
* 计划的环保分级：无铅 (RoHS)、无铅（RoHS 豁免）或绿色环保（RoHS 和无 Sb/Br）- 请单击上表中产品目录明细的“查看”链接，以获得最新供货信息和附加产品目录明细。
如果此时没有在线提供您所请求的信息，则请联系 我们的产品信息中心， 以了解关于此信息可用性的信息。
XIO2213A 最新技术文档 
| 名称 | 型号 | 公司 | 工具/软件类型 |
| 开发电路板/EVM | XIO2213AEVM | Texas Instruments | 开发电路板/EVM |
| 型号 | 名称 | 产品系列 | 注释 |
| TSB83AA23 | TSB83AA23 IEEE Std 1394b-2002 | 器件与被比较器件具有相似功能，但并不功能等效。 Base GPN is PCI Express, Alternative is PCI | |
| TSB83AA22C | IEEE 标准 1394b-2002 PHY 和 OHCI 链路器件 | 器件与被比较器件具有相似功能，但并不功能等效。 Base GPN is PCI Express, Alternative is PCI | |
| TSB81BA3D | IEEE P1394b 三端电缆收发器/仲裁器 | 器件与被比较器件具有相似功能，但并不功能等效。 This product contains only the 1394b Physical Layer |
