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电压转换器和电平转换器
应用特定的电压转换器

SN74LVC161284

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具有三态输出的 19 位总线接口

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数据表

SN74LVC161284

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数据表 立即订购

产品详情

Technology family LVC Applications IEEE1284 Rating Catalog Operating temperature range (°C) 0 to 70
Technology family LVC Applications IEEE1284 Rating Catalog Operating temperature range (°C) 0 to 70
SSOP (DL) 48 164.358 mm² 15.88 x 10.35 TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1
  • 1.4-k Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Designed for the IEEE Std 1284-I (Level 1 Type) and IEEE Std 1284-II (Level 2 Type) Electrical Specifications
  • Flow-Through Architecture Optimizes PCB Layout
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin-Shrink Small-Outline (DGG) Packages
  • 1.4-k Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Designed for the IEEE Std 1284-I (Level 1 Type) and IEEE Std 1284-II (Level 2 Type) Electrical Specifications
  • Flow-Through Architecture Optimizes PCB Layout
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin-Shrink Small-Outline (DGG) Packages

The SN74LVC161284 is designed for 3-V to 3.6-V VCC operation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.

This device has eight bidirectional bits; data can flow in the A-to-B direction when DIR is high, and in the B-to-A direction when DIR is low. This device also has five drivers, which drive the cable side, and four receivers. The SN74LVC161284 has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line.

The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level 1 type) and IEEE Std 1284-II (level 2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and PERI LOGIC OUT, all cable-side pins have a 1.4-k integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low state or if the output voltage is above VCC CABLE. If VCC CABLE is off, PERI LOGIC OUT is set to low.

The device has two supply voltages. VCC is designed for 3-V to 3.6-V operation. VCC CABLE supplies the inputs and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even when VCC CABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant.

The SN74LVC161284 is characterized for operation from 0°C to 70°C.

The SN74LVC161284 is designed for 3-V to 3.6-V VCC operation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.

This device has eight bidirectional bits; data can flow in the A-to-B direction when DIR is high, and in the B-to-A direction when DIR is low. This device also has five drivers, which drive the cable side, and four receivers. The SN74LVC161284 has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line.

The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level 1 type) and IEEE Std 1284-II (level 2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and PERI LOGIC OUT, all cable-side pins have a 1.4-k integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low state or if the output voltage is above VCC CABLE. If VCC CABLE is off, PERI LOGIC OUT is set to low.

The device has two supply voltages. VCC is designed for 3-V to 3.6-V operation. VCC CABLE supplies the inputs and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even when VCC CABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant.

The SN74LVC161284 is characterized for operation from 0°C to 70°C.
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类型 标题 下载最新的英语版本 日期
* 数据表 SN74LVC161284 数据表 (Rev. J) 2005年 2月 15日
应用手册 Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
选择指南 Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
选择指南 Little Logic Guide 2018 (Rev. G) 2018年 7月 6日
选择指南 Logic Guide (Rev. AB) 2017年 6月 12日
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应用手册 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
选择指南 逻辑器件指南 2014 (Rev. AA) 最新英语版本 (Rev.AB) 2014年 11月 17日
选择指南 小尺寸逻辑器件指南 (Rev. E) 最新英语版本 (Rev.G) 2012年 7月 16日
用户指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
应用手册 CMOS 非缓冲反向器在振荡器电路中的使用 英语版 2006年 3月 23日
应用手册 选择正确的电平转换解决方案 (Rev. A) 英语版 (Rev.A) 2006年 3月 23日
产品概述 Design Summary for WCSP Little Logic (Rev. B) 2004年 11月 4日
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用户指南 Signal Switch Data Book (Rev. A) 2003年 11月 14日
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应用手册 LVC Characterization Information 1996年 12月 1日
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设计指南 Low-Voltage Logic (LVC) Designer's Guide 1996年 9月 1日
应用手册 Understanding Advanced Bus-Interface Products Design Guide 1996年 5月 1日

设计和开发

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仿真模型

HSPICE Model for SN74LVC161284

SCEJ258.ZIP (102 KB) - HSpice Model
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仿真模型

SN74LVC161284 IBIS Model

SCAM032.ZIP (100 KB) - IBIS Model
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封装 引脚 下载
SSOP (DL) 48 查看选项
TSSOP (DGG) 48 查看选项
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订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

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