CDCLVP1102
- 1:2 Differential Buffer
- Single Clock Input
- Universal Inputs Can Accept LVPECL, LVDS,
LVCMOS/LVTTL - Two LVPECL Outputs
- Maximum Clock Frequency: 2 GHz
- Maximum Core Current Consumption: 33 mA
- Very Low Additive Jitter: <100 fs, RMS in 10-kHz
to 20-MHz Offset Range - 2.375-V to 3.6-V Device Power Supply
- Maximum Propagation Delay: 450 ps
- Maximum Output Skew: 10 ps
- LVPECL Reference Voltage, VAC_REF, Available
for Capacitive-Coupled Inputs - Industrial Temperature Range: –40°C to 85°C
- Supports 105°C PCB Temperature
(Measured at Thermal Pad) - Available in 3-mm × 3-mm QFN-16 (RGT) Package
- ESD Protection Exceeds 2 kV (HBM)
The CDCLVP1102 is a highly versatile, low additive jitter buffer that can generate two copies of LVPECL clock outputs from one LVPECL, LVDS, or LVCMOS input for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 10 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP1102 clock buffer distributes a single clock input (IN) to two pairs of differential LVPECL clock outputs (OUT0, OUT1) with minimum skew for clock distribution. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP1102 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
The CDCLVP1102 is characterized for operation from 40°C to 85°C and is available in a QFN-16, 3-mm × 3-mm package.
技术文档
类型 | 标题 | 下载最新的英语版本 | 日期 | |||
---|---|---|---|---|---|---|
* | 数据表 | CDCLVP1102 Two-LVPECL Output, High-Performance Clock Buffer 数据表 (Rev. D) | PDF | HTML | 2015年 12月 11日 | ||
EVM 用户指南 | CDCLVP1102EVM User's Guide | 2009年 7月 9日 |
设计和开发
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CDCLVP1102EVM — CDCLVP1102 评估模块
CDCLVP1102 是一款高性能、低附加相位噪声时钟缓冲器。它具有单个通用输入缓冲器,支持单端或差动时钟输入,并且可馈给 2 个 LVPECL 输出。该器件还具有片上偏压发生器,它可以为器件输入提供 LVPECL 共模电压。此评估模块 (EVM) 旨在演示 CDCLVP1102 的电性能。这个完全组装且经过工厂测试的评估板允许对 CDCLVP1102 器件的所有功能进行全面验证。为达到最佳性能,该评估板配备有 50W SMA 连接器和受控良好的 50W 阻抗微带传输线。
CLOCK-TREE-ARCHITECT — 时钟树架构编程软件
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封装 | 引脚 | 下载 |
---|---|---|
VQFN (RGT) | 16 | 查看选项 |
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