CDCLVP1204
- 2:4 Differential Buffer
- Selectable Clock Inputs Through Control Terminal
- Universal Inputs Accept LVPECL, LVDS, and
LVCMOS/LVTTL - Four LVPECL Outputs
- Maximum Clock Frequency: 2 GHz
- Maximum Core Current Consumption: 45 mA
- Very Low Additive Jitter: <100 fs, RMS in 10-kHz
to 20-MHz Offset Range:- 57 fs, RMS (typical) at 122.88 MHz
- 48 fs, RMS (typical) at 156.25 MHz
- 30 fs, RMS (typical) at 312.5 MHz
- 2.375-V to 3.6-V Device Power Supply
- Maximum Propagation Delay: 450 ps
- Maximum Output Skew: 15 ps
- LVPECL Reference Voltage, VAC_REF, Available
for Capacitive-Coupled Inputs - Industrial Temperature Range: –40°C to +85°C
- Supports 105°C PCB Temperature (Measured at
Thermal Pad) - ESD Protection Exceeds 2 kV (HBM)
The CDCLVP1204 is a highly versatile, low additive jitter buffer that can generate four copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1204 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control terminal. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 15 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP1204 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to four pairs of differential LVPECL clock outputs (OUT0, OUT3) with minimum skew for clock distribution. The CDCLVP1204 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP1204 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) must be applied to the unused negative input terminal. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
The CDCLVP1204 is characterized for operation from –40°C to +85°C.
技术文档
类型 | 标题 | 下载最新的英语版本 | 日期 | |||
---|---|---|---|---|---|---|
* | 数据表 | CDCLVP1204 Four LVPECL Output, High-Performance Clock Buffer 数据表 (Rev. F) | PDF | HTML | 2015年 9月 3日 | ||
用户指南 | CDCLVP1204 User's Guide | 2009年 7月 9日 |
设计和开发
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CDCLVP1204EVM — CDCLVP1204 评估模块
CDCLVP1204 是一款高性能、低附加相位噪声时钟缓冲器。它具有两个通用输入缓冲器,支持单端或差动时钟输入,可通过控制引脚进行选择。该器件还具有片上偏压发生器,它可以为器件输入提供 LVPECL 共模电压。此评估模块 (EVM) 旨在演示 CDCLVP1204 的电性能。这个完全组装且经过工厂测试的评估板允许对 CDCLVP1204 的所有功能进行全面验证。为达到最佳性能,该评估板配备有 50Ω SMA 连接器和受控良好的 50Ω 阻抗微带传输线。
CLOCK-TREE-ARCHITECT — 时钟树架构编程软件
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封装 | 引脚 | 下载 |
---|---|---|
VQFN (RGT) | 16 | 查看选项 |
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- 引脚镀层/焊球材料
- MSL 等级/回流焊峰值温度
- MTBF/时基故障估算
- 材料成分
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- 封装厂地点
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